Data Sheet
Functionality: quad transmitters, quad receivers,
and dual observation receivers with 2 inputs each
Bandwidth: 200 MHz receiver,
200 MHz large signal/ 450 MHz synthesis transmitter
,and 450 MHz observation receiver
Tuning range: 650 MHz to 6 GHz
Interface: 12 Gbps JESD204B/C 1
Power consumption: 5 W 2
Multichip LO phase synchronization
DFE features: Enhanced DPD / CLGC / CFR 3
Package: 14 ×14 BGA
1. Will update to 24.33Gbps in future release
2. For 25% Rx 75% Tx, 1x Orx on, 200 MHz/450 MHz/450MHz BW, 0 dB attenuation
3. Supported on ADRV9029 which is coming soon
Product Details
ADRV9029 reference design for small cell
On board RF reference design
▪ Add PA pre-driver stage HMC625B/ADL5611 to enable the reference platform can connect to PA EVB directly
▪ Add ADI RF Front end products ADRF5545A/ADRF5549 on RX channels, and switch products on ORx channels
▪ Make the board support middle/high RF bands simultaneously
On board clock solution
▪ Use dual clock domains clock device AD9545
▪ Add SyncE capability needed for O-RAN
On board power supply solution
▪ Use ADP5054 as the power supply for ADRV902x and clock devices
▪ Leave interface for external PoE EVB + ADI power brick supply
Multiple FPGA platform supported
▪ Work with either ADS9 board or Intel Arria 10 board.
▪ Common GUI software and user interface
DFE verification software supported
▪ Integrate the DPD / CFR / CLGC verification interface in GUI
